Navid Payvadosi

Navid Paydavosi is a seasoned hardware engineer with a decade of experience in advanced Si process technology and GPU and memory subsystem optimization. He excels in optimizing PPAC for complex SoC systems. He holds a Ph.D. in Electrical Engineerig from the University of Alberta and completed a postdoctoral scholarship at UC Berkeley under supervision of Prof. Chenming Hu, contributing to the development of FinFET and SOI SPICE compact models. Navid began his Intel career in 2014 as a Logic Technology Development Device Engineer, where he contributed to key advancements in Intel 4 and Intel 3 technology nodes. He then served as a GPU Micro-Arch Power Optimization Engineer, leading innovations such as a novel Glitch minimization algorithm. As a NAND Flash Power and Performance Optimization Engineer, Navid significantly improved the power and performance of Intel's 3D NAND Flash products. Currently, he is a Senior Staff Intel Foundry Device Engineer, customizing the Intel 3 technology node for customers. Navid's expertise spans device physics, semiconductor manufacturing, and power optimization. His goal is to deliver world-class AI hardware solutions for Data Center and Edge computing environments.