Below the 90nm technology node, printability problems inherent in the process technology have become the major yield detractor of integrated circuit manufacture. Due to inevitable process variations, especially focus and exposure variations in the optical lithography process, many parts of a design layout have bridging, necking or line-end shortening problems after being printed which can cause the circuits to fail certain specifications and therefore become yield detractors. These parts are defined as hotspots. Design rule checking (DRC) was developed to help circuit designers to detect such potential yield detractors by specifying geometric and connectivity restrictions which ensure sufficient margins to account for process variations, but the ever increasing number of rules needed as we move to more advanced technology nodes is becoming cumbersome to maintain. This dissertation proposes a new design hotspot classification and detection system that classifies hotspots based on geometric similarity (defined in the context of lithographic pattern transfer), identifies the common type of failure of each hotspot class, stores a compact description of each hotspot class in a library, and feeds this library to a pattern-matching tool for fast hotspot detection in new design layouts. This approach offers several advantages over standard DRC. Generation of the library of hotspot classes is completely automatic and offline, and it can be automatically updated for variant processes or more advanced technology nodes. The library can be embedded into current design tools and function together with standard DRC. Detection of problematic patterns in a layout using pattern matching is fast. Finally, this approach could lead to automated hotspot corrections that exploit the similarities of hotspots occupying the same cluster. The dissertation provides details of the implementation of the proposed hotspot classification and detection system, and presents proof of concept results. First, hotspots such as pinching/bridging are recognized in a full-scale IC layout based on thorough process simulations. Small layout "snippets" centered on hotspots are clipped from the layout and similarities between these snippets are calculated by computing their overlapping areas. This is accomplished using an efficient, rectangle-based algorithm. The snippet overlapping areas can be weighted by a function derived from the optical parameters of the lithography process. Second, these hotspots are clustered using a novel, efficient incremental clustering algorithm. Finally, each cluster is analyzed in order to identify the common cause of failure for all the hotspots in that cluster, and its representative pattern is fed to a pattern-matching tool for detecting similar hotspots in new design layouts. Thus, the long list of hotspots is reduced to a small number of meaningful clusters and a library of characterized hotspot types is produced that can be updated upon getting new hotspot types. This hotspot classification and detection system also has the potential capability of driving automatic and efficient hotspot corrections, which could lead to a much shorter design to manufacturing development cycle.