Suitable for a one- or two-semester undergraduate or beginning graduate course in computer science and computer engineering, Computer Organization, Design, and Architecture, Fourth Edition presents the operating principles, capabilities, and limitations of digital computers to enable development of complex yet efficient systems. With 40% updated material and four new chapters, this edition takes students through a solid, up-to-date exploration of single- and multiple-processor systems, embedded architectures, and performance evaluation. New to the Fourth Edition Additional material that covers the ACM/IEEE computer science and engineering curricula More coverage on computer organization, embedded systems, networks, and performance evaluation Expanded discussions of RISC, CISC, VLIW, and parallel/pipelined architectures The latest information on integrated circuit technologies and devices, memory hierarchy, and storage Updated examples, references, and problems Supplying appendices with relevant details of integrated circuits reprinted from vendors’ manuals, this book provides all of the necessary information to program and design a computer system.

Table of Contents:
Introduction Computer System Organization Computer Evolution Organization vs. Design vs. Architecture Performance Evaluation Number Systems and Codes Number Systems Conversion Arithmetic Sign-Magnitude System Complement Number System Floating-Point Numbers Binary Codes Data Storage and Register Transfer Representation of Numbers, Arrays, and Records Combinational Logic Basic Operations and Terminology Boolean Algebra (Switching Algebra) Minimization of Boolean Functions Primitive Hardware Blocks Functional Analysis of Combinational Circuits Synthesis of Combinational Circuits Some Popular Combinational Circuits Integrated Circuits Loading and Timing Synchronous Sequential Circuits Flip-Flops Timing Characteristics of Flip-Flops Flip-Flop ICS Analysis of Synchronous Sequential Circuits Design of Synchronous Sequential Circuits Registers Register Transfer Logic Register Transfer Schemes Register Transfer Languages Designing Sequential Circuits with Integrated Circuits Programmable Logic A Simple Computer: Organization and Programming A Simple Computer ASC Assembler Program Loading Subroutines Macros Linkers and Loaders A Simple Computer: Hardware Design Program Execution Data, Instruction, and Address Flow Bus Structure Arithmetic and Logic Unit Input/Output Control Unit Console Microprogrammed Control Unit Input/Output General I/O Model The I/O Function Interrupts Direct Memory Access Bus Architecture Channels I/O Processors (IOP) Serial I/O Common I/O Devices Examples Processor and Instruction Set Architectures Types of Computer Systems Operand (Data) Types and Formats Registers Instruction Set Addressing Modes Instruction Set Orthoganality RISC vs. CISC Example Systems Memory and Storage Types of Memory Memory System Parameters Memory Hierarchy Memory Devices and Organizations Memory System Design Using ICS Speed Enhancement Size Enhancement Address Extension Example Systems Arithmetic/Logic Unit Enhancement Logical and Fixed-Point Binary Operations Decimal Arithmetic Pipelining ALU with Multiple Functional Units Example Systems Control Unit Enhancement Speed Enhancement Hardwired vs. Microprogrammed Control Units Pipeline Performance Issues Example Systems Advanced Architectures MISD SIMD MIMD Cache Coherence Data-Flow Architectures Systolic Architectures Example Systems Embedded Systems Characteristics Software Architectures Operating System (OS) Example Systems Computer Networks and Distributed Processing Computer Networks Distributed Processing Grid Computing Performance Evaluation Performance Measures Cost Factor Benchmarks Code Optimization Appendix A: Details of Representative Integrated Circuits Gates, Decoders, and Other ICS Useful in Combinational Circuit Design Flip-Flops, Registers, and Other ICS Useful in Sequential Circuit Design Memory ICS Appendix B: Stack Implementation INDEX A Summary, References, and Problems appear at the end of each chapter.