Table of Contents:
1. Introduction.- 1.1. From nMOS to CMOS.- 1.2. CMOS Basic Gates.- 2. MOS Transistor Characteristics.- 2.1. The MOS Transistor.- 2.2. Parasitic Parameters.- 2.3. Small Geometry MOS Transistor.- 2.4. CMOS Transmission Gate.- 2.5. CMOS Inverter.- 2.6. A More Accurate Model for the CMOS Inverter.- 2.7. CMOS Power Dissipation.- 3. Fabrication Processes.- 3.1. The p-well Fabrication Process.- 3.2. The n-well Fabrication Process.- 3.3. LOCMOS Technology.- 3.4. Latchup.- 3.5. The Twin-tub Fabrication Process.- 3.6. The SOS Fabrication Process.- 3.7. Bulk vs. SOI.- 3.8. Design Rules.- 4. Logic Design.- 4.1. Static Logic.- 4.1.1. Complementary Logic.- 4.1.2. nMOS-like Logic.- 4.1.3. Transmission Gate Intensive Logic.- 4.1.4. Cascode Logic.- 4.2. Dynamic Logic.- 4.2.1. Ripple-through Logic.- 4.2.2. P-ELogic.- 4.2.3. Clocked CMOS Logic.- 4.2.4. Domino Logic.- 4.2.5. NORA Logic.- 4.3. Charge Sharing.- 4.4. Bootstrap Logic.- 4.5. Logic Design at the System Level.- 5. Circuit Design.- 5.1. Resistance, Capacitance, and Inductance.- 5.1.1. Interconnect Resistance.- 5.1.2. Interconnect Capacitance.- 5.1.3. Interconnect Inductance.- 5.1.4. Interconnect Discontinuities.- 5.1.5. Coupling Parameters and Interconnect Delay.- 5.1.6. Diffusion Resistance.- 5.1.7. Contact Resistance.- 5.2. Modeling Long Interconnects.- 5.3. The Concept of Equivalent Gate Load.- 5.4. Delay Minimization.- 5.4.1. Inverter Delay and Sizing.- 5.4.2. Inverter Chain Sizing.- 5.4.3. Inverter Chain Sizing with Stray Capacitance.- 5.5. Transistor Sizing in Static Logic.- 5.6. Transistor Sizing in Dynamic Logic.- 6. Design of Basic Circuits.- 6.1. Storage Elements.- 6.2. Full-adder.- 6.3. Programmable Logic Array.- 6.4. Random-access Memory.- 6.4.1. Memory Cell.- 6.4.2. Decoder.- 6.4.3. Sense Amplifier.- 6.5. Parallel Adder.- 6.6. Parallel Multiplier.- 6.6.1. The Design of a Multiplier Based on the Modified Booth Algorithm.- 6.6.2. Basic Building-blocks Inside the Array.- 6.6.3. The Problem of Sign Extension.- 6.6.3.1. The "Sign Propagate" Method.- 6.6.3.2. The "Sign Generate" Method.- 6.6.4. The Implementation of a 24-bit CMOS Booth Multiplier.- 7. Driver and I/O Buffer Design.- 7.1. CMOS Inverter Delay Estimation.- 7.1.1. Fall-time Delay Estimation.- 7.1.1.1. Region 1: n-channel Device in Saturation.- 7.1.1.2. Region 2: n-channel Device in Linear Region.- 7.1.2. Rise-time Delay Estimation.- 7.1.3. Refining the Model.- 7.2. Input Buffer.- 7.3. Output Buffer.- 7.4. Tri-state Output Buffer and I/O Buffer.- 7.5. Output Buffer and Bus Driver Design Optimization.- 7.5.1. Unconstrained Delay Minimization.- 7.5.2. Constrained Delay Minimization.- 7.6. Input Protection.- 7.7. Output Protection.- 7.8. Driving Large On-chip Loads.- Appendix A. Layout.- A. 1. General Considerations on Layout.- A.2. Layout Methodologies for Latchup Avoidance.- A.3. Layout with Structured Methodologies.- A. 4. Power and Ground Routing.- Appendix B. Interconnect Capacitance Computation.- B. 1. Case 1: Coupled Microstrip Structure.- B.2. Case 2: Coupled Stripline Structure.- Appendix C. Figures from Section 5.4.2.- Appendix D. Delay Minimization Based on Eq. (7-3).- Appendix E. Equations Related to Fig. 7-10.- Appendix F. Symbols and Physical Constants.