The Definitive, Up-to-Date Guide to Digital Design with SystemVerilog: Concepts, Techniques, and Code To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)—and today’s most powerful, useful HDL is SystemVerilog, now an IEEE standard. Digital System Design with SystemVerilog is the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it. Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog—from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org. Coverage includes Using electronic design automation tools with programmable logic and ASIC technologies Essential principles of Boolean algebra and combinational logic design, with discussions of timing and hazards Core modeling techniques: combinational building blocks, buffers, decoders, encoders, multiplexers, adders, and parity checkers Sequential building blocks: latches, flip- flops, registers, counters, memory, and sequential multipliers Designing finite state machines: from ASM chart to D flip-flops, next state, and output logic Modeling interfaces and packages with SystemVerilog Designing testbenches: architecture, constrained random test generation, and assertion-based verification Describing RTL and FPGA synthesis models Understanding and implementing Design-for-Test Exploring anomalous behavior in asynchronous sequential circuits Performing Verilog-AMS and mixed-signal modeling Whatever your experience with digital design, older versions of Verilog, or VHDL, this book will help you discover SystemVerilog’s full power and use it to the fullest.

Table of Contents:
List of Figures      xiii List of Tables      xix Preface      xxi Acknowledgments      xxvii About the Author      xxix Chapter 1: Introduction      1 1.1 Modern Digital Design 1 1.2 Designing with Hardware Description Languages 2 1.3 CMOS Technology 8 1.4 Programmable Logic 16 1.5 Electrical Properties 19 Summary 22 Further Reading 22 Exercises 23 Chapter 2: Combinational Logic Design      25 2.1 Boolean Algebra 25 2.2 Logic Gates 29 2.3 Combinational Logic Design 30 2.4 Timing 37 2.5 Number Codes 40 Summary 43 Further Reading 44 Exercises 44 Chapter 3: Combinational Logic Using SystemVerilog Gate Models      47 3.1 Modules and Files 47 3.2 Identifiers, Spaces, and Comments 48 3.3 Basic Gate Models 50 3.4 A Simple Netlist 51 3.5 Logic Values 52 3.6 Continuous Assignments 52 3.7 Delays 53 3.8 Parameters 56 3.9 Testbenches 56 Summary 58 Further Reading 58 Exercises 58 Chapter 4: Combinational Building Blocks      61 4.1 Multiplexers 61 4.2 Decoders 63 4.3 Priority Encoder 68 4.4 Adders 69 4.5 Parity Checker 72 4.6 Three-State Buffers 73 4.6.1 Multi-Valued Logic 73 4.7 Testbenches for Combinational Blocks 74 Summary 76 Further Reading 76 Exercises 76 Chapter 5: SystemVerilog Models of Sequential Logic Blocks      79 5.1 Latches 79 5.2 Flip-Flops 82 5.3 JK and T Flip-Flops 86 5.4 Registers and Shift Registers 88 5.5 Counters 90 5.6 Memory 97 5.7 Sequential Multiplier 100 5.8 Testbenches for Sequential Building Blocks 102 Summary 106 Further Reading 106 Exercises 106 Chapter 6: Synchronous Sequential Design      109 6.1 Synchronous Sequential Systems 109 6.2 Models of Synchronous Sequential Systems 110 6.3 Algorithmic State Machines 114 6.4 Synthesis from ASM Charts 119 6.5 State Machines in SystemVerilog 129 6.6 Testbenches for State Machines 137 Summary 138 Further Reading 138 Exercises 138 Chapter 7: Complex Sequential Systems      143 7.1 Linked State Machines 143 7.2 Datapath/Controller Partitioning 147 7.3 Instructions 150 7.4 A Simple Microprocessor 151 7.5 SystemVerilog Model of a Simple Microprocessor 156 Summary 165 Further Reading 165 Exercises 165 Chapter 8: Writing Testbenches      167 8.1 Basic Testbenches 168 8.2 Testbench Structure 170 8.3 Constrained Random Stimulus Generation 174 8.4 Assertion-Based Verification 178 Summary 182 Further Reading 183 Exercises 183 Chapter 9: SystemVerilog Simulation      185 9.1 Event-Driven Simulation 185 9.2 SystemVerilog Simulation 189 9.3 Races 192 9.4 Delay Models 194 9.5 Simulator Tools 195 Summary 196 Further Reading 196 Exercises 196 Chapter 10: SystemVerilog Synthesis      199 10.1 RTL Synthesis 200 10.2 Constraints 210 10.3 Synthesis for FPGAs 216 10.4 Behavioral Synthesis 218 10.5 Verifying Synthesis Results 225 Summary 228 Further Reading 228 Exercises 228 Chapter 11: Testing Digital Systems      231 11.1 The Need for Testing 231 11.2 Fault Models 232 11.3 Fault-Oriented Test Pattern Generation 234 11.4 Fault Simulation 242 Summary 246 Further Reading 246 Exercises 247 Chapter 12: Design for Testability      251 12.1 Ad hoc Testability Improvements 252 12.2 Structured Design for Test 253 12.3 Built-In Self-Test 255 12.4 Boundary Scan (IEEE 1149.1) 264 Summary 272 Further Reading 272 Exercises 272 Chapter 13: Asynchronous Sequential Design      277 13.1 Asynchronous Circuits 277 13.2 Analysis of Asynchronous Circuits 281 13.3 Design of Asynchronous Circuits 285 13.4 Asynchronous State Machines 293 13.5 Setup and Hold Times and Metastability 297 Summary 302 Further Reading 302 Exercises 302 Chapter 14: Interfacing with the AnalogWorld      305 14.1 Digital-to-Analog Converters 306 14.2 Analog-to-Digital Converters 307 14.3 Verilog-AMS 310 14.4 Phased-Locked Loops 319 14.5 Verilog-AMS Simulators 323 Summary 323 Further Reading 324 Exercises 324 Appendix A: SystemVerilog and Verilog      325 A.1 Standards 325 A.2 SystemVerilog and Verilog Differences 326 Answers to Selected Exercises      331 Bibliography      347 Index      349