The Practical, Start-to-Finish Guide to Modern Digital Design Verification As digital logic designs grow larger and more complex, functional verification has become the number one bottleneck in the design process. Reducing verification time is crucial to project success, yet many practicing engineers have had little formal training in verification, and little exposure to the newest solutions. Hardware Design Verification systematically presents today's most valuable simulation-based and formal verification techniques, helping test and design engineers choose the best approach for each project, quickly gain confidence in their designs, and move into fabrication far more rapidly. College students will find that coverage of verification principles and common industry practices will help them prepare for jobs as future verification engineers. Author William K. Lam, one of the world's leading experts in design verification, is a recent winner of the Chairman's Award for Innovation, Sun Microsystems' most prestigious technical achievement award. Drawing on his wide-ranging experience, he introduces the foundational principles of verification, presents traditional techniques that have survived the test of time, and introduces emerging techniques for today's most challenging designs. Throughout, Lam emphasizes practical examples rather than mathematical proofs; wherever advanced math is essential, he explains it clearly and accessibly. Coverage includes Simulation-based versus formal verification: advantages, disadvantages, and tradeoffs Coding for verification: functional and timing correctness, syntactical and structure checks, simulation performance, and more Simulator architectures and operations, including event-driven, cycle-based, hybrid, and hardware-based simulators Testbench organization, design, and tools: creating a fast, efficient test environment Test scenarios and assertion: planning, test cases, test generators, commercial and Verilog assertions, and more Ensuring complete coverage, including code, parameters, functions, items, and cross-coverage The verification cycle: failure capture, scope reduction, bug tracking, simulation data dumping, isolation of underlying causes, revision control, regression, release mechanisms, and tape-out criteria An accessible introduction to the mathematics and algorithms of formal verification, from Boolean functions to state-machine equivalence and graph algorithms Decision diagrams, equivalence checking, and symbolic simulation Model checking and symbolic computation Simply put, Hardware Design Verification will help you improve and accelerate your entire verification process--from planning through tape-out--so you can get to market faster with higher quality designs.

Table of Contents:
Preface xvii Acknowledgments xxiii About the Author xxv Chapter 1 An Invitation to Design Verification 1 1.1 What Is Design Verification? 2 1.2 The Basic Verification Principle 4 1.3 Verification Methodology 8 1.4 Simulation-Based Verification versus Formal Verification 15 1.5 Limitations of Formal Verification 17 1.6 A Quick Overview of Verilog Scheduling and Execution Semantics 17 1.7 Summary 23 Chapter 2 Coding for Verification 25 2.1 Functional Correctness 27 2.2 Timing Correctness 39 2.3 Simulation Performance 44 2.4 Portability and Maintainability 52 2.5 "Synthesizability," "Debugability," and General Tool Compatibility 56 2.6 Cycle-Based Simulation 59 2.7 Hardware Simulation/Emulation 62 2.8 Two-State and Four-State Simulation 64 2.9 Design and Use of a Linter 66 2.10 Summary 67 2.11 Problems 67 Chapter 3 Simulator Architectures and Operations 73 3.1 The Compilers 74 3.2 The Simulators 79 3.3 Simulator Taxonomy and Comparison 108 3.4 Simulator Operations and Applications 112 3.5 Incremental Compilation 126 3.6 Summary 129 3.7 Problems 130 Chapter 4 Test Bench Organization and Design 137 4.1 Anatomy of a Test Bench and a Test Environment 137 4.2 Initialization Mechanism 142 4.3 Clock Generation and Synchronization 148 4.4 Stimulus Generation 155 4.5 Response Assessment 162 4.6 Verification Utility 183 4.7 Test Bench-to-Design Interface 195 4.8 Common Practical Techniques and Methodologies 196 4.9 Summary 204 4.10 Problems 204 Chapter 5 Test Scenarios, Assertions, and Coverage 211 5.1 Hierarchical Verification 214 5.2 Test Plan 217 5.3 Pseudorandom Test Generator 227 5.4 Assertions 232 5.5 SystemVerilog Assertions 248 5.6 Verification Coverage 259 5.7 Summary 279 5.8 Problems 280 Chapter 6 Debugging Process and Verification Cycle 287 6.1 Failure Capture, Scope Reduction, and Bug Tracking 288 6.2 Simulation Data Dumping 297 6.3 Isolation of Underlying Causes 300 6.4 Design Update and Maintenance: Revision Control 315 6.5 Regression, Release Mechanism, and Tape-out Criteria 318 6.6 Summary 321 6.7 Problems 322 Chapter 7 Formal Verification Preliminaries 331 7.1 Sets and Operations 332 7.2 Relation, Partition, Partially Ordered Set, and Lattice 334 7.3 Boolean Functions and Representations 342 7.4 Boolean Functional Operators 353 7.5 Finite-State Automata and Languages 359 7.6 Summary 380 7.7 Problems 381 Chapter 8 Decision Diagrams, Equivalence Checking, and Symbolic Simulation 387 8.1 Binary Decision Diagrams 388 8.2 Decision Diagram Variants 412 8.3 Decision Diagram-Based Equivalence Checking 424 8.4 Boolean Satisfiability 430 8.5 Symbolic Simulation 442 8.6 Summary 457 8.7 Problems 458 Chapter 9 Model Checking and Symbolic Computation 465 9.1 Properties, Specifications, and Logic 466 9.2 Property Checking 484 9.3 Symbolic Computation and Model Checking 494 9.4 Symbolic CTL Model Checking 513 9.5 Computational Improvements 524 9.6 Using Model-Checking Tools 529 9.7 Summary 531 9.8 Problems 531 Bibliography 539 Index 561