Welcome to the proceedings of PATMOS 2008, the 18th in a series of int- national workshops. PATMOS 2008 was organized by INESC-ID / IST - TU Lisbon, Portugal, with sponsorship by Cadence, IBM, Chipidea, and Tecmic, and technical co-sponsorship by the IEEE. Over the years, PATMOS has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design meth- ologies, and tools required for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2008 c- tained state-of-the-art technical contributions, three invited talks, and a special session on recon?gurable architectures. The technical program focused on t- ing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and op- mization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 41 papers presented at PATMOS. The papers were - ganized into 7 oral sessions (with a total of 31 papers) and 2 poster sessions (with a total of 10 papers). As is customary for the PATMOS workshops, full papers were required for review, and a minimum of three reviews were received per manuscript.

Table of Contents:
Session 1: Low-Leakage and Subthreshold Circuits.- Subthreshold FIR Filter Architecture for Ultra Low Power Applications.- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs.- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction.- Session 2: Low-Power Methods and Models.- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction.- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.- Power-Aware Design via Micro-architectural Link to Implementation.- Untraditional Approach to Computer Energy Reduction.- Session 3: Arithmetic and Memories.- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication.- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length.- A Design Space Comparison of 6T and 8T SRAM Core-Cells.- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization.- Session 4: Variability and Statistical Timing.- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.- A Study on CMOS Time Uncertainty with Technology Scaling.- Static Timing Model Extraction for Combinational Circuits.- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA.- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power.- Session 5: Synchronization and Interconnect.- Logic Synthesis of Handshake Components Using Structural Clustering Techniques.- Fast Universal Synchronizers.- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router.- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.- Session 6: Power Supplies and Switching Noise.- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits.- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint.- Generating Worst-Case Stimuli for Accurate Power Grid Analysis.- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization.- Session 7: Low-Power Circuits; Reconfigurable Architectures.- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.- Energy Efficient Elliptic Curve Processor.- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.- Poster Session 1: Circuits and Methods.- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.- Ultra Low Voltage High Speed Differential CMOS Inverter.- Differential Capacitance Analysis.- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.- Poster Session 2: Power and Delay Modeling.- Analytical High-Level Power Model for LUT-Based Components.- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption.- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.- Data Dependence of Delay Distribution for a Planar Bus.- Special Session: Power Optimizations Addressing Reconfigurable Architectures.- Towards Novel Approaches in Design Automation for FPGA Power Optimization.- Smart Enumeration: A Systematic Approach to Exhaustive Search.- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor.- Keynotes (Abstracts).- Integration of Power Management Units onto the SoC.- Model to Hardware Matching for nm Scale Technologies.- Power and Profit: Engineering in the Envelope.