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VHDL for Engineers POD/NR

VHDL for Engineers

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About the Book
This book teaches readers how to design and simulate digital systems using the hardware description language, VHDL. Focus is placed on writing VHDL design decriptions, VHDL testbenches, and the steps in VHDL/PLD (programmable logic devices) design methodology. KEY TOPICS: Topics include: Digital Design using VHDL and PLDs; Entities, Architectures, and Coding Styles; Signals and Data Types; Dataflow and Behavioral Style Combinational Design; Event-Driven Simulation; Testbenches for Combinational Designs; Latches and Flip-Flops; Mulitbit Latches, Registers, Counters, and Memory; Finite State Machines; ASM Charts and RTL Design; Subprograms; Packages; Testbenches for Sequential Systems; Modular Design and Hierarchy. More than 275 block diagrams, logic diagrams, and timing waveforms and 180+ program listings illustrate the design concepts. The book includes the Aldec Active-HDL(TM) 7.2 Student Edition Software.

MARKET: This book is suitable for anyone with a basic understanding of logic design and a minimal background in programming who desires to lean how to design digital systems using VHDL. No prior experience with VHDL is required.

Book Details
ISBN-13: 9780131424784
Publisher: Pearson
Publisher Imprint: Pearson
Depth: 32
Height: 242 mm
No of Pages: 685
Series Title: English
Weight: 1259 gr
ISBN-10: 0131424785
Publisher Date: 01 Apr 2008
Binding: Mixed media product
Edition: 1 HAR/CDR
Language: English
Returnable: N
Spine Width: 32 mm
Width: 187 mm
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