Acceleration of parallel applications using hardware co-processors has been lately receiving rising attention in both academia and industry. Architectures based on reconfigurable hardware, graphical processors, and multi/many-core processors have been adopted. One example of such architectures is that of the High-Performance Reconfigurable Computers (HPRCs), that are parallel computers but with added FPGA chips as hardware co-processors or accelerators. Examples of such systems are the Cray XD1, the Cray XT5 h, the SRC-6, the SRC-7, and the SGI Altix/RASC. Harnessing the high-performance of such systems requires parallel processing and/or multitasking. An executing process under such scenarios requires access to a conventional processing power, assisted by a reconfigurable resource. However, different architectures may have conventional and reconfigurable resources integrated in different ways and proportions, resulting in highly imbalanced heterogeneous systems. Thus, using a new HPRC is a new challenge and porting applications across HPRCs requires substantial efforts. In order to promote ease-of-use and portability, for software developers, it is necessary to virtualize (or abstract) these architectures, such that higher levels in the system hardware-software stack are presented with a consistent balanced architectural view. Such view would be one of a system of conventional processors, each accelerated with its own reconfigurable resource. Such virtualization system will then be responsible for mapping the user virtual resource requests into physical ones without the user's knowledge. This requires a hardware abstraction layer that is capable of virtualizing reconfigurable resources through scheduling, sharing and aggregation techniques. In an HPRC, such an abstraction layer cannot be only software and should be realized as a hardware-software co-design that can leverage partial run-time reconfiguration. This research work: (1) Proposes a hardware virtualization framework to resolve the ease-of-use and portability issues in HPRCs. The virtualization framework is based on Partial Run-Time Reconfiguration (PRTR), reconfigurable resource allocation and scheduling. (2) Provides guidelines for efficient mapping of the framework into HPRC system hardware and software. (3) Proposes an analytical modeling technique for design space exploration in order to predict the parameters of a virtualized framework that can meet the design goals, based on Markov chains and queuing networks. The proposed framework was prototyped on a modern HPRC, the Cray XD1 at HPCL, and extensive experimental results were obtained. While the proposed system is intended for improving user productivity, namely programmability and portability, the results show that it can also achieve substantial increase in performance. This is because virtualization can transparently leverage partial run-time reconfiguration and thus reduce the full configuration overhead. Furthermore, the experimental results were also in agreement with the analytical model.