The summer school on VLSf GAD Tools and Applications was held from July 21 through August 1, 1986 at Beatenberg in the beautiful Bernese Oberland in Switzerland. The meeting was given under the auspices of IFIP WG 10. 6 VLSI, and it was sponsored by the Swiss Federal Institute of Technology Zurich, Switzerland. Eighty-one professionals were invited to participate in the summer school, including 18 lecturers. The 81 participants came from the following countries: Australia (1), Denmark (1), Federal Republic of Germany (12), France (3), Italy (4), Norway (1), South Korea (1), Sweden (5), United Kingdom (1), United States of America (13), and Switzerland (39). Our goal in the planning for the summer school was to introduce the audience into the realities of CAD tools and their applications to VLSI design. This book contains articles by all 18 invited speakers that lectured at the summer school. The reader should realize that it was not intended to publish a textbook. However, the chapters in this book are more or less self-contained treatments of the particular subjects. Chapters 1 and 2 give a broad introduction to VLSI Design. Simulation tools and their algorithmic foundations are treated in Chapters 3 to 5 and 17. Chapters 6 to 9 provide an excellent treatment of modern layout tools. The use of CAD tools and trends in the design of 32-bit microprocessors are the topics of Chapters 10 through 16. Important aspects in VLSI testing and testing strategies are given in Chapters 18 and 19.

Table of Contents:
1 VLSI Design Strategies.- 1.1 Introduction.- 1.2 VLSI Complexity.- 1.3 The Design Spectrum.- 1.4 The Role of CAD Tools.- 1.5 The Role of the Designer.- 1.6 The Synthesis Project at Berkeley.- 1.7 Conclusions.- 1.8 References.- 2 Introduction to VLSI Design.- 2.1 Introduction.- 2.2 The MOS Transistor.- 2.3 Inverter Circuits.- 2.4 Generalized Inverter Circuits.- 2.5 Transmission Gates.- 2.6 Full Adders.- 2.7 Programmed Logic Arrays.- 2.8 Clocked Circuits.- 2.9 Finite-State Machines.- 2.10 Integrated Circuit Fabrication.- 2.11 Design Rules.- 2.12 References.- 3 Simulation Tools for VLSI.- 3.1 Introduction.- 3.2 Circuit-Level Simulation.- 3.3 A Linear Model for MOS Networks.- 3.4 A Switch Model for MOS Networks.- 3.5 Gate-Level Simulation.- 3.6 References.- 4 Aspects of Computational Circuit Analysis.- 4.1 Introduction.- 4.2 Formulation of the Circuit Equations.- 4.3 Table Representations of Devices.- 4.4 Linear Algebra Techniques.- 4.5 Newton-Like Methods.- 4.6 Continuation Methods.- 4.7 Time-integration Schemes.- 4.8 Macromodeling of Circuits.- 4.9 References.- 5 VLSI Circuit Analysis, Timing Verification and Optimization.- 5.1 Introduction.- 5.2 Circuit Analysis.- 5.3 Timing Verification.- 5.4 Circuit Optimization.- 5.5 References.- 6 CAD Tools for Mask Generation.- 6.1 Introduction.- 6.2 Advantages.- 6.3 Mechanisms.- 6.4 ABCD.- 6.5 Design Capture.- 6.6 Compaction.- 6.7 Technology Encapsulation.- 6.8 Software Engineering.- 7 Design and Layout Generation at the Symbolic Level.- 7.1 Introduction.- 7.2 The Role of Symbolic Representation.- 7.3 EDISTIX.- 7.4 TOPOGEN.- 7.5 ZORRO.- 7.6 Conclusions.- 7.7 Acknowledgements.- 7.8 References.- 8 Overview of the IDA System: A Toolset for VLSI Layout Synthesis.- 8.1 Introduction and Background.- 8.2 Key Ideas in IDA.- 8.3 IMAGES: aSymbolic, Constraint-Based Generator Design Language.- 8.4 Compaction and Assembly.- 8.5 Layout Synthesis.- 8.6 Other Tools and Features of IDA.- 8.7 Summary.- 8.8 References.- 9 CAD Programming in an Object Oriented Programming Environment.- 9.1 Introduction.- 9.2 The Programming Environment.- 9.3 The Organization of NS.- 9.4 Design Verification in NS.- 9.5 Physical Design in NS.- 9.6 History and Results.- 9.7 References.- 10 Trends in Commercial VLSI Microprocessor Design.- 10.1 Introduction.- 10.2 Historical Design Practice.- 10.3 Current Design Practice Details.- 10.4 Future Designs.- 10.5 Forecast.- 10.6 Summary.- 10.7 References.- 11 Experience with CAD Tools for a 32-Bit VLSI Microprocessor.- 11.1 Introduction.- 11.2 Top Down Simulation.- 11.3 The Interpreter.- 11.4 Architectural Simulator.- 11.5 Functional Simulator.- 11.6 Schematic Logic Drawings: Draw.- 11.7 Switch Level Simulation: Soisim.- 11.8 Backporting: Switch Level Simulation Without Vector Files.- 11.9 Layout Tools: Mulga.- 11.10 Circuit Extraction: Goalie.- 11.11 Netlist Comparison: Gemini.- 11.12 Timing Analysis: ADVICE and Leadout.- 11.13 Naming Conventions.- 11.14 Control the Source Code.- 11.15 UNIX.- 11.16 Some Statistics.- 11.17 Weak Spots.- 11.18 Results.- 11.19 Conclusion.- 11.20 References.- 12 Overview of a 32-Bit Microprocessor Design Project.- 12.1 Introduction.- 12.2 Processor Description.- 12.3 High Level Decisions and Influences.- 12.4 Design Tools.- 12.5 Division of Labor.- 12.6 Problems.- 12.7 Important Results and Conclusions.- 12.8 References.- 13 Architecture of Modern VLSI Processors.- 13.1 Introduction.- 13.2 Microprocessor Architecture Design Considerations.- 13.3 Memory Management Architectures.- 13.4 Memory Interfacing Peripherals.- 13.5 Summary.- 13.6 Acknowledgments.- 13.7 References.- 14 A Comparison of Microprocessor Architectures in View of Code Generation by a Compiler.- 14.1 Introduction.- 14.2 The Target Architectures and Their Instruction Formats.- 14.3 Code Generation.- 14.4 Measurements.- 14.5 Conclusions.- 14.6 References.- 15 Fault Tolerant VLSI Multicomputers.- 15.1 Introduction.- 15.2 Fault Tolerance.- 15.3 Self-Checking Nodes.- 15.4 Defects and Faults in VLSI.- 15.5 Self-Testing Comparators in VLSI.- 15.6 Implementation Issues.- 15.7 System Level Protocols.- 15.8 Conclusions.- 15.9 References.- 16 The VLSI Design Automation Assistant: An IBM System/370 Design.- 16.0 Introduction.- 16.1 Conception.- 16.2 Birth.- 16.3 First Steps.- 16.4 The IBM System/370 Experiment.- 16.5 Summary.- 16.6 References.- 17 Higher Level Simulation and CHDLs.- 17.1 Introduction: Why CHDLs?.- 17.2 Early Phases of the Design Process.- 17.3 Introducing a CHDL and Its Use.- 17.4 CHDL-based Design Environments.- 17.5 Conclusions.- 17.6 Literature.- 18 New Trends in VLSI Testing.- 18.1 Introduction.- 18.2 The Test Assembler.- 18.3 The Test Advisor.- 18.4 Interface with the General Data Base.- 18.5 Conclusion.- 18.6 References.- 19 VLSI Testing: DFT Strategies and CAD Tools.- 19.1 Introduction.- 19.2 DFT Strategies.- 19.3 CAD-Tools.- 19.4 Conclusions.- 19.5 Literature.