VLSI Design is intended to serve as a comprehensive textbook for undergraduate students of engineering. It seeks to provide a thorough understanding of the fundamental concepts and design of VLSI systems. The book starts by providing a historical perspective as well as design methodologies of VLSI systems. It then proceeds on to describe the various concepts of VLSI such as SCLD and its characterization, MOS Transistors, Analog and Digital CMOS Logic Designs, and BiCMOS Technology and Circuits. Detailed description of Hardware Description Languages such as VHDL and Verilog is covered before taking up an exhaustive, step-wise discussion on the various stages involved in designing a VLSI chip (that includes logic synthesis, timing analysis, floor planning, placement and routing, verification, and testing). The book also contains seperate chapters on FPGA including its architecture, and important softwares such as Xilinx, IRSIM, and GOSPL and VLSI Process Technology. Written in a lucid manner, the book contains numerous examples and illustrations supporting the text. Exercises in the form of MCQs and review questions, including both short and long answer type questions are provided at the end of every chapter. An appendix on the tutorial on SPICE is provided to enhance the understanding of designing and simulation of circuits.

Table of Contents:
1. Introduction to VLSI Systems ; 1.1 Historical Perspective ; 1.2 Introduction to IC technology ; 1.3 VLSI Design Methodology ; 1.4 Y-chart ; 1.4.1 VLSI Design Flow ; 1.5 Design Hierarchy ; 1.5.1 Regularity, Modularity, and Locality ; 1.5.2 VLSI Design Styles ; 1.5.3 FPGA ; 1.5.4 Gate Array Design ; 1.5.5 Standard-cell Based Design ; 1.6 Full-custom Design ; 1.7 Semi-custom Design ; 1.7.1 Computer-Aided Design ; 1.7.2 System Design - algorithmic level ; 1.7.3 Logic Design - structural level ; 1.7.4 Circuit design - transistor level ; 1.7.5 Physical Design - layout level ; 1.8 Design verification ; REFERENCES ; 2. MOS Transistor ; 2.1 Introduction to MOS Transistor ; 2.2 Structure and operation of MOSFET ; N-MOS ENHANCEMENT TYPE ; 2.3 p-MOS enhancement type ; 2.4 n-MOS depletion type ; P-MOS DEPLETION TYPE ; 2.5 MOS current equation ; 2.5.1 MOSFET V-I characteristics ; 2.6 MOS transistor threshold Voltage, gm, gds, figure of merit ; 2.7 MOSFET scaling ; 2.7.1 Small geometry effects ; 2.7.2 MOSFET capacitances ; 2.7.3 Modeling of MOS Transistors ; 2.8 Basic concept the SPICE level-1 model ; 2.9 level -2 model ; LEVEL -3 MODEL ; 3. Standard Cell Library Design and Characterization ; 3.1 Introduction ; 3.1.1 Standard Core Cells ; 3.1.2 I/O Cells ; 3.2 Schematic Design ; 3.2.1 Examples ; 3.3 Layout Design ; 3.3.1 Stick Diagram ; 3.3.2 Design Rules ; 3.3.3 MOSIS Design Rules ; 3.3.4 Micron Rules ; 3.3.5 Design Rule Checking (DRC) ; 3.4 Layout vs. Schematic (LVS) ; 3.5 Device Extraction ; 3.6 Parasitic Extraction ; 3.6.1 Parasitic Capacitance Estimation ; 3.6.2 Parasitic Resistance Estimation ; 3.7 Antenna Effect ; 3.7.1 Antenna Rules ; 3.8 Contents of Standard cell library ; 3.9 Library Characterization ; 3.9.1 Design Margin ; 3.9.2 Supply Voltage ; 3.9.3 Temperature ; 3.9.4 Process Variation ; 3.9.5 Design Corners ; 3.10 Cell Characterization ; 3.11 Circuit Simulation ; EXAMPLE - CMOS INVERTER ; TRANSIENT RESPONSE ; TRANSFER CHARACTERISTICS ; 3.12 Measuring Propagation Delay ; 3.13 Measuring Rise/Fall Times ; 3.14 Ring oscillator ; 3.15 Timing Characterization - Load slew characterization ; 3.16 Power characterization ; 3.16.1 Dynamic Power Consumption ; 3.16.2 Power dissipation due to short-circuit current ; 3.16.3 Static or Leakage power dissipation ; 3.17 Power Delay Product (PDP) ; 3.18 Energy Delay Product (EDP) ; 3.19 Power and Energy measurement ; 3.20 Reliability and Noise Characterization ; 3.20.1 Crosstalk Noise Analysis ; 3.20.2 Electromigration (EM) Analysis ; 3.20.3 Gate Oxide Integrity (GOI) Analysis ; 3.20.4 Channel Hot Carrier (CHC) Analysis ; 3.21 Interconnect Delay Modeling ; 3.21.1 RC delay model ; 3.21.2 Elmore delay model ; 3.21.3 Transmission line model ; 4. Analog CMOS Design ; 4.1 Basic Building Blocks ; 4.2 MOS Switches ; 4.3 MOS diode ; 4.4 MOS current source and sink ; 4.5 Current mirror ; 4.6 Resistor realization using Switched Capacitor ; 4.7 Voltage level shifter ; 4.8 MOS Voltage and Current references ; 4.9 CMOS amplifier ; 4.10 MOS Differential Amplifier ; 4.11 Cascode amplifier ; 4.12 Current amplifier ; 4.13 Output Amplifier ; 4.14 Source follower ; 4.15 CMOS Operational Amplifier ; 4.16 Design of CMOS OPAMP ; 4.17 Compensation ; 4.18 Design of two-stage OPAMP ; 4.19 Cascade OPAMP ; 4.20 Comparator ; 4.21 Switched Capacitor Filter ; 4.22 ADC ; 4.22.1 Flash ADC ; 4.22.2 Delta-Sigma Modulator ; 4.23 DAC ; 4.24 Phase locked Loop ; 4.25 FPAA ; 5. Digital CMOS Logic design ; 5.1 Introduction to Digital Logic Design ; 5.2 Introduction to CMOS Logic Design ; 5.3 CMOS design methodology ; 5.4 Design of CMOS Inverter ; 5.5 Design of Two-input NAND gate ; 5.6 Design of Two-input NOR gate ; 5.7 Classification of CMOS Digital Logic Circuit ; 5.8 Combinational Logic Circuit ; 5.8.1 Complex Logic Circuit ; 5.8.2 Design of XOR gate ; 5.8.3 Half-Adder Circuit ; 5.8.4 Full-Adder Circuit ; EXAMPLE - DESIGN OF AOI GATE ; EXAMPLE - DESIGN OF TRI-STATE BUFFER ; EXAMPLE - DESIGN OF MULTIPLEXER ; 5.9 Sequential Logic Circuit ; 5.9.1 SR Latch Circuit ; 5.9.2 Clocked Latch and Flip-flop circuit ; 5.9.3 Clocked JK Latch ; 5.10 Pseudo NMOS Logic ; 5.11 CMOS Transmission Logic ; 5.11.1 Design of Combinational Logic Circuits using CMOS TGs ; 5.12 D-Latch and Edge-Triggered Flip-flop ; 5.13 Dynamic CMOS Logic ; 5.14 Domino CMOS Logic ; 5.15 NORA CMOS Logic ; 5.16 Zipper CMOS Logic ; TRUE SINGLE PHASE CLOCK (TSPC) DYNAMIC CMOS ; 5.17 Pass Transistor Logic (PTL) ; EXAMPLE OF PTL ; 5.18 Complementary Pass Transistor (CPL) ; EXAMPLE OF CPL ; 5.19 Differential CMOS Logic - CVSL ; 5.20 Adiabatic Logic ; 5.21 Dual threshold CMOS Logic ; 5.22 Tally circuits - NAND-NAND, NOR-NOR, AOI Logic ; 5.23 Semiconductor Memories ; 5.23.1 SRAM ; 5.23.2 DRAM ; 5.23.3 ROM ; 5.23.4 Flash memory ; 6. BiCOMS Technology and Circuits ; 6.1 BiCMOS Technology ; 6.2 BiCMOS Logic ; 6.3 BiCMOS Circuits ; 6.3.1 I-V characteristics ; 6.4 BiCMOS inverter ; 6.5 BiCMOS NAND ; 6.6 BiCMOS NOR ; 7. VHDL ; 7.1 Introduction to VHDL ; 7.2 Case study - Full adder ; 7.2.1 Structural modeling ; 7.2.2 Dataflow modeling ; 7.2.3 Behavioral modeling ; 7.2.4 Mixed modeling ; 7.3 Datapath design ; 7.3.1 Adder ; 7.3.1.1 Half adder ; 7.3.1.2 Test bench of half adder ; 7.3.1.3 Full Adder ; 7.3.1.4 Serial Adder ; 7.3.1.5 Parallel Adder - Ripple Carry Adder ; 7.3.1.6 Carry look-ahead adder (CLA) ; 7.3.1.7 n-bit Adder ; 7.3.2 Subtractor ; 7.3.2.1 Half subtractor ; 7.3.2.2 Full subtractor ; 7.3.3 Adder/subtractor circuit ; 7.3.4 Multiplier ; 7.3.4.1 Unsigned Array Multiplier ; 7.3.4.2 Signed Binary Multiplier ; 7.3.5 Divider ; 7.3.6 Counter ; 7.3.7 Comparator ; 7.3.8 Zero/one detector ; 7.3.8.1 VHDL program for Zero detector ; 7.3.8.2 VHDL Program for One detector ; 7.3.9 Parity Generator and Checker ; 7.3.9.1 Even Parity Generator ; 7.3.9.2 Even Parity Checker ; 7.4 Memory ; 7.4.1 Read Write Memory - RAM ; 7.4.2 Read Only Memory - ROM ; 7.5 Barrel shifter ; 7.6 Arithmetic Logic Unit (ALU) ; 7.7 VHDL Language ; 7.7.1 Basic Language Syntax ; 7.7.2 Data Objects ; 7.7.2.1 Syntax for data objects ; 7.7.2.2 Signal Data object ; .7.7.2.3 Constant Data objects ; 7.7.2.4 Variable Data Objects ; 7.7.2.5 File Data Objects ; 7.7.2.6 Other Data Objects ; 7.7.3 Data Object Values ; 7.7.4 Data Types ; 7.7.4.1 BIT and BIT_VECTOR types ; 7.7.4.2 STD_LOGIC and STD_LOGIC_VECTOR types ; 7.7.4.3 STD_ULOGIC type ; 7.7.4.4 SIGNED and UNSIGNED types ; 7.7.4.5 INTERGER type ; 7.7.4.6 BOOLEAN type ; 7.7.4.7 ENUMERATION type ; 7.7.4.8 FLOATING POINT type ; 7.7.4.9 PHYSICAL types ; 7.7.1.10 ARRAY type ; 7.7.4.11 FILE type ; 7.7.5 Operators in VHDL ; 7.7.5.1 Boolean Operators ; 7.7.5.2 Arithmetic Operators ; 7.7.5.3 Shift Operators ; 7.7.5.4 Relational Operators ; 7.7.5.5 Miscellaneous operators ; 7.7.5.6 Operator Precedence ; 7.7.6 Hardware modeling ; 7.7.6.1 Entity declaration ; 7.7.6.2 Architecture body ; 7.7.6.3 Signal assignment statement ; 7.7.6.3.1 Default delay ; 7.7.6.4 Variable assignment statement ; 7.7.6.5 Wait statement ; 7.7.7 Component declaration ; 7.7.8 Component instantiation ; 7.7.9 Generic declaration ; 7.7.10 Statements in VHDL ; 7.7.10.1 Concurrent statements ; 7.7.10.2 Concurrent signal assignment statement ; 7.7.10.3 Conditional signal assignment statement ; 7.7.10.4 Selected signal assignment statement ; 7.7.10.5 Block statement ; 7.7.10.6 Concurrent assertion statement ; 7.7.10.7 Sequential statements ; 7.7.10.8 Process statement ; 7.7.10.9 If statement ; 7.7.10.10 Case statement ; 7.7.10.11 Generate statement ; 7.7.10.12 If generate statement ; 7.7.10.13 Select statement ; 7.7.10.14 Loop statement ; 7.7.10.15 Exit statement ; 7.7.10.16 Next statement ; 7.7.10.17 Assertion statement ; 7.7.10.18 Report statement ; 7.7.11 Library ; 7.7.12 Package ; 7.7.13 Using Library and Package in VHDL ; 8. Verilog ; 8.1 Verilog modeling ; 8.2 Verilog Syntax ; 8.2.1 Some other Verilog syntax ; 8.3 Operator in Verilog ; 8.4 Verilog Data Types ; 8.5 Numbers in Verilog ; 8.5.1 Integer Constants ; 8.5.2 Real Constants ; 8.5.3 Negative Numbers ; 8.6 Strings ; 8.7 Four-Value Logic ; 8.8 Behavioral modeling ; 8.8.1 Behavioral modeling using Boolean Expression ; 8.8.2 Propagation Delay ; 8.9 Structural modeling ; 8.10 Delay modeling in Verilog ; 8.10.1 Inertial Delay ; 8.10.2 Transport Delay ; 8.10.3 Min:Nom:Max Delay Modeling in Verilog ; 8.11 Truth Table Model with Verilog (User Defined Primitive - UDP) ; 8.12 Assignment statements ; 8.13 Sequential Block ; 8.14 Wait Statement ; 8.15 Procedures in Verilog ; 8.16 Control statements ; 8.17 Case Statement ; 8.18 Loop Statement ; 8.19 Disable Statement ; 8.20 If Statement ; 8.21 Combinational logic in Verilog ; 8.22 Sequential logic in Verilog ; 8.23 Modeling edge-sensitive flip-flops ; 8.24 Blocking and Non-blocking Assignment statement ; 8.25 Finite State Machines (FSM) ; 8.26 Test Benches in Verilog ; EXAMPLES ; 9. Logic Synthesis ; 9.1 Introduction ; 9.2 Transistor level Synthesis ; 9.3 Logic level Synthesis ; 9.4 Block level Synthesis ; 9.5 Logic Synthesis ; 9.5.1 Logic Synthesis Steps ; 9.6 Design Styles ; 9.7 Logic Synthesis Tools ; 9.8 Logic Synthesis Goals ; 9.9 Algorithms ; 9.9.1 Boolean Algebra ; 9.9.2 Boole's Expansion Theorem ; 9.9.3 Tabular Method ; 9.10 Terminology ; 9.11 Binary Decision Diagram (BDD) ; 9.11.1 Ordered Binary Decision Diagram (OBDD) ; 9.11.2 Reduced Ordered Binary Decision Diagram (ROBDD) ; 9.11.3 Variable Ordering ; 9.11.4 Applications of BDD ; 9.12 Logic Synthesis Advantages ; 9.13 Disadvantages of Logic Synthesis ; 9.14 How does it work ; 9.15 Sequential Logic Optimization ; 9.15.1 State Minimization ; 9.15.2 State Encoding ; 9.16 Logic Synthesis using Multiplexer ; TYPE - 0 , TYPE - 1 , TYPE - 2 , TYPE - 3 DESIGN ; 10. Timing analysis ; INTRODUCTION ; 10.1 Delay of Any System ; 10.2 Delay in VLSI circuits ; 10.3 Delay in CMOS Inverter ; 10.4 Slew Balancing ; 10.5 Transistor Equivalency ; 10.6 Effect of Transistor Size on Delay ; 10.7 Design of Two-input NAND Gate ; 10.8 Design of Two-input NOR Gate ; 10.9 MOS Capacitances ; 10.9.1 Gate Capacitance ; 10.9.2 Junction Capacitances ; 10.9.3 MOS Transistor Capacitances ; 10.9.4 Effective Load Capacitance ; 10.10 Effect of Power Supply Voltage on Delay ; 10.11 Design Techniques for Delay Reduction ; 10.12 Intrinsic Delay of Inverter ; 10.13 Inverter Sizing Effect on Delay ; 10.14 Inverter Chain Design - Super Buffer ; 10.15 Effect of Slew on Delay ; 10.16 Delay Dependency of Input Patterns ; 10.17 Logical Effort ; 10.18 Classification of Digital Systems ; 10.19 Synchronous Digital Design ; 10.20 Timing - Definitions ; 10.21 Timing Analysis ; 10.22 Timing Models ; 10.23 Timing Analysis Goals ; 10.24 Timing Analysis at the Chip Level ; 10.25 Static timing analysis (STA) vs. Dynamic timing analysis ; 10.26 Factors Impacting Delay ; 10.27 STA - Case Study ; 10.27.1 Delay Graph ; 10.27.2 Computing Signal Timing ; 10.28 Fixed Delay Model ; 10.29 Checking Timing Constraints ; 10.29.1 Computing Latest Signal Arrival Times ; 10.29.2 Straightforward Extensions ; 10.29.3 Computing Latest Signal Required Times ; 10.29.4 Computing Slack at node V ; 10.29.5 Detecting False paths ; 10.29.6 When can a Path be False? ; 10.29.7 Intentional False Paths ; 10.30 Timing verification in Sequential Synchronous Circuits ; 10.30.1 Timing Constraints at Flip-Flops ; 10.30.2 Flip-Flop Constraints with Clock Skew ; 10.30.3 Clock Jitter ; 10.31 Hierarchical Timing Specification and Verification ; 10.32 Issues with Static Delay Modeling ; 10.33 First-order Gate Delay Model ; 10.34 Parasitic Extraction ; 10.35 Timing Convergence Problem ; 10.35.1 Approaches to Timing Convergence ; 10.36 Timing-driven Logic Synthesis Problem ; 10.37 Gate and Device Sizing ; 10.38 Typical Delay-Area tradeoff ; 10.39 Timing-driven Layout Synthesis ; 11. Physical Design (Floor planning, Placement, and Routing) ; 11.1 Floorplanning Goals ; 11.2 Floorplanning Inputs ; 11.3 Floorplanning Objectives ; 11.4 Floorplanning Classes ; 11.4.1 Slicing Floorplan ; 11.4.2 Non-slicing Floorplan ; 11.5 Abutment ; 11.6 Hierarchical Floorplanning ; 11.7 Floorplanning Algorithms ; 11.7.1 Sizing Algorithm for Slicing Floorplans ; 11.7.2 Polish expression ; 11.7.3 Simulated annealing ; 11.7.4 Wong-Liu algorithm ; 11.7.5 Shape Function Evaluation ; 11.7.5 Genetic Algorithm for Floorplanning ; 11.8 I/O and Power planning ; 11.9 Clock planning ; 11.10 Delay estimation during floorplanning ; 11.11 Floorplanning Guidelines ; 11.12 Placement ; 11.13 Placement Goals and Objectives ; 11.14 Placement algorithms ; 11.14.1 Constructive Placement ; 11.14.2 Iterative placement ; 11.15 Partitioning ; 11.15.1 Kernighan-Lin algorithm ; 11.16 Timing Driven Placement ; 11.17 Congestion driven placement ; 11.18 Layout compaction ; 11.19 Wire length estimation ; 11.20 Routing ; 11.21 Goals and objectives ; 11.22 Global routing ; 11.23 Detail routing ; 11.24 Clock routing ; 11.25 Channel routing ; 11.26 Inter cell routing ; 11.27 Maze routing ; 11.28 Algorithms ; 11.29 Crosstalk aware routing ; 11.30 Timing driven routing ; 11.31 Routing constraints ; 11.32 CAD Tools for Physical design ; 11.33 Layout database ; 11.33.1 DEF ; 11.33.2 LEF ; 11.33.3 GDSII ; 12. Layout Verification and Reliability Check ; 12.1 Layout Design Rules ; 12.2 Lamda rules ; 12.3 Mead Conway rules ; 12.4 Design Rule Check ; 12.5 Layout extraction ; 12.6 Device extraction ; 12.7 Parasitic extraction ; 12.8 Layout vs. schematic check ; 12.9 Open-short check ; 12.10 Connectivity check ; 12.11 Timing verification ; 12.12 Crosstalk analysis ; 12.13 Crosstalk Glitch ; 12.14 Crosstalk delay ; RELIABILITY ; 12.15 Introduction ; 12.16 IC Reliability ; 12.17 Electromigration ; 12.17.1 Power EM ; 12.17.2 Signal EM ; 12.18 Time Dependent Dielectric Breakdown (TDDB) ; 12.18.1 Overshoot/undershoot due to crosstalk ; 12.18.2 Miller effect ; 12.18.3 Overshoot/undershoot due to Ldi/dt effect ; 12.19 Channel Hot Electron (CHC) ; 12.20 Negative Bias Temperature Instability (NBTI) ; 12.21 Power and ground bounce ; 12.22 IR drop ; 12.23 Latch-up ; 12.24 ESD and EOS ; 12.24.1 ESD Models ; 12.24.2 ESD Failures ; 12.24.3 ESD Protection Circuit ; 12.25 Soft error ; 13. IC Packaging ; 13.1 Types of package ; 13.2 Package modeling ; 13.2.1 Electrical ; 13.2.2 Thermal ; 13.2.3 Stress ; 13.3 Package Models ; 13.3.1 IBIS ; 13.3.2 SPICE ; 13.4 Package simulation ; 13.5 CAD tools ; 13.6 Examples ; 13.7 Flip-chip package ; 14. VLSI Testing ; 14.1 Introduction ; 14.2 Test - Importance ; 14.3 Fault models ; 14.3.1 Stuck at fault ; 14.4 Fault simulation ; 14.4.1 Deterministic fault simulation ; 14.4.1.1 Serial Fault Simulation ; 14.4.1.2 Parallel Fault Simulation ; 14.4.1.3 Concurrent Fault Simulation ; 14.4.2 Nondeterministic Fault Simulation ; 14.5 Design for Testability (DFT) ; 14.5.1 Controllability and Observability ; 14.6 Ad-hoc testing ; 14.7 Scan Test ; 14.7.1 Serial Scan Test ; 14.7.2 Parallel Scan ; 14.8 Boundary Scan Test ; 14.9 Built-in Self Test (BIST) ; 14.9.1 Linear Feedback Shift Register ; 14.9.2 Signature Analyzer ; 14.9.3 Built-in Logic Block Observer ; 14.10 Automatic Test-Pattern Generation (ATPG) ; 14.11 IDDQ Test ; 14.12 Design for Manufacturability ; 14.12.1 Optimizing Physical layout ; 14.12.2 Introducing Redundancy ; 14.12.3 Minimizing Power dissipation ; 14.12.4 Wide Process modeling ; 14.12.5 Yield Analysis ; 14.13 Design Economics ; 14.14 Yield ; 14.15 Probe Test ; 15. FPGA ; 15.1 Introduction ; 15.2 FPGA Architecture ; 15.3 Principle of FPGA based System design ; 15.4 Programmable Logic Devices (PLD) ; 15.5 PLA ; 15.6 PAL ; 15.7 CPLD ; 15.8 ASIC ; 15.9 Introduction to Xilinx ; 15.10 IRSIM ; 15.11 GOSPL ; 16. VLSI Process Technology ; 16.1 Crystal growth ; 16.1.1 Silicon crystal growth ; 16.1.1.1 Czochralski technique ; 16.1.1.2 Dopant distribution ; 16.1.2 Float-zone technique ; 16.1.3 Bridgman technique ; 16.2 Wafer preparation ; 16.2.1 Characterization ; 16.2.2 Mobility ; 16.2.3 Hall effect ; 16.2.4 Haynes-Shockley experiment ; 16.2.5 Lifetime Measurement ; 16.2.6 Resistivity ; 16.2.6.1 Four probe technique ; 16.3 Photo Lithography ; 16.3.1 Exposure Techniques ; 16.3.2 Comparison between different exposure systems ; 16.3.3 Clean room ; 16.3.4 Mask ; 16.3.5 Resolution Enhancement Techniques (RET) ; 16.3.5.1 Phase shift mask ; 16.3.5.2 Alternate Phase-Shifting ; 16.3.5.3 Halftone (or Attenuated) Phase-Shifting ; 16.3.5.4 Optical proximity correction ; 16.3.6 Photo resist ; 16.3.7 Pattern generation ; 16.4 Oxidation ; 16.4.1 Dry oxidation ; 16.4.2 Wet oxidation ; 16.4.3 Chemical Vapor Deposition (CVD) ; 16.6.4 Thin oxide ; 16.6.5 Thick oxide ; 16.7 Diffusion ; 16.7.1 Fick's law ; 16.7.2 Diffusion profile ; 16.8 Ion implantation ; 16.8.1 Ion stopping ; 16.8.2 Ion channeling ; 16.8.3 Damage and annealing ; 16.9 Etching ; 16.9.1 Wet chemical etching ; 16.9.2 Dry etching ; 16.9.3 Plasma etching ; 16.9.4 Reactive ion etching ; 16.10 Epitaxial growth ; 16.10.1 Chemical vapor deposition (CVD) ; 16.10.2 MOCVD ; 16.10.3 MBE ; 16.10.4 Physical vapor deposition ; 16.11 Metallization ; 16.12 Packaging ; 16.12.1 Die separation ; 16.12.2 Package types ; 16.12.3 Wire Bonding ; 16.12.4 Tape-automated bonding ; 16.12.5 Flip chip bonding ; APPENDIX A ; A.1 TUTORIAL ON SPICE ; A.2 WRITING SPICE NETLIST ; A.3 SYNTAX FOR CIRCUIT DESCRIPTION ; A.4 EXAMPLES ; A.5 ANALYSIS TYPES IN SPICE ; A.5.1 DC ANALYSIS ; A.5.2 AC ANALYSIS ; A.5.3 TRANSIENT ANALYSIS ; A.6 SPECIFYING VOLTAGE SOURCES IN SPICE ; A.6.1 DC SOURCE ; A.6.2 AC SOURCE ; A.6.3 VOLTAGE SOURCE OF PULSE TYPE ; A.6.4 PIECE-WISE LINEAR (PWL) VOLTAGE SOURCE ; A.6.5 VOLTAGE SOURCE WITH BIT PATTERN ; A.7 SPECIFYING MODEL PARAMETERS ; A.8 USING SUBCKT IN SPICE ; A.8.1 EXAMPLE OF SUBCKT ; A.9 OTHER USEFUL STATEMENTS IN SPICE