Home > Science, Technology & Agriculture > Electronics and communications engineering > Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package(IEEE Press)
41%
Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package(IEEE Press)

Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package(IEEE Press)

          
5
4
3
2
1

International Edition


Premium quality
Premium quality
Bookswagon upholds the quality by delivering untarnished books. Quality, services and satisfaction are everything for us!
Easy Return
Easy return
Not satisfied with this product! Keep it in original condition and packaging to avail easy return policy.
Certified product
Certified product
First impression is the last impression! Address the book’s certification page, ISBN, publisher’s name, copyright page and print quality.
Secure Checkout
Secure checkout
Security at its finest! Login, browse, purchase and pay, every step is safe and secured.
Money back guarantee
Money-back guarantee:
It’s all about customers! For any kind of bad experience with the product, get your actual amount back after returning the product.
On time delivery
On-time delivery
At your doorstep on time! Get this book delivered without any delay.
Quantity:
Add to Wishlist

About the Book

Discover an up-to-date exploration of Embedded and Fan-Out Waver and Panel Level technologies In Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package, a team of accomplished semiconductor experts delivers an in-depth treatment of various fan-out and embedded die approaches. The book begins with a market analysis of the latest technology trends in Fan-Out and Wafer Level Packaging before moving on to a cost analysis of these solutions. The contributors discuss the new package types for advanced application spaces being created by companies like TSMC, Deca Technologies, and ASE Group. Finally, emerging technologies from academia are explored. Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces is an indispensable resource for microelectronic package engineers, managers, and decision makers working with OEMs and IDMs. It is also a must-read for professors and graduate students working in microelectronics packaging research.

Table of Contents:
Preface xv 1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends 1 Santosh Kumar, Favier Shoo, and Stephane Elisabeth 1.1 Introduction to Fan-Out Packaging 1 1.1.1 Historical Perspective 1 1.1.2 Key Drivers: Why Fan-Out Packaging? 6 1.1.3 FO-WLP vs. FO-PLP 8 1.1.4 Future of Fan-Out Packaging for Heterogeneous Integration 8 1.2 Market Overview and Applications 10 1.2.1 Fan-Out Packaging Definition 10 1.2.2 Market Segmentation: Core FO vs. HD FO vs. UHD FO 11 1.2.3 Market Valuation: Forecast of Revenue and Volume 12 1.2.4 Current and Future Target Markets 12 1.2.5 Applications of Fan-Out Packaging 14 1.3 Technology Trends and Supply Chain 19 1.3.1 Fan-Out Packaging Technology Roadmaps 19 1.3.2 Fan-Out Packaging Technology by Manufacturer 19 1.3.2.1 Amkor 19 1.3.2.2 JCET 20 1.3.2.3 NXP 21 1.3.2.4 DECA Technologies 21 1.3.2.5 ASE 22 1.3.2.6 TSMC 22 1.3.2.7 PTI 24 1.3.2.8 Samsung Electronics 25 1.3.2.9 Huatian 25 1.3.3 Supply Chain Overview 25 1.3.4 Analysis of the Latest Developments in the Supply Chain 26 1.4 Fan-Out Panel-Level Packaging (FO-PLP) 29 1.4.1 Motivation and Challenges for FO-PLP 29 1.4.2 FO-PLP Market and Applications 30 1.4.3 FO-PLP Supplier Overview 31 1.5 SystemDevice Teardowns 34 1.5.1 Teardown of End-Systems with Fan-Out Packaging 34 1.5.2 Technology Comparison 38 1.5.2.1 Radar IC: eWLB vs. RCP 38 1.5.2.2 MCM/SiP: RCP-SiP vs. eWLB 39 1.5.2.3 PMIC: eWLB vs. M-Series 40 1.5.3 Cost Comparison 41 1.6 Conclusion 42 References 45 2 Cost Comparison of FO-WLP with Other Technologies 47 Amy Palesko Lujan 2.1 Introduction 47 2.2 Activity-Based Cost Modeling 47 2.3 Cost Analysis of FO-WLP Variations 49 2.3.1 Process Segment Costs 50 2.3.1.1 Die Preparation 50 2.3.1.2 Carrier 50 2.3.1.3 Die Bond 51 2.3.1.4 Mold 51 2.3.1.5 Backgrinding 51 2.3.1.6 RDL 51 2.3.1.7 UBM 52 2.3.1.8 Flux and Ball Attach 52 2.3.1.9 Singulation 52 2.3.2 FO-WLP Variations 52 2.3.2.1 Carrier 54 2.3.2.2 Die Cost and Preparation 54 2.3.2.3 Die Bond 54 2.3.2.4 Mold/Mold+CUF 54 2.3.2.5 Backgrind/Post-mold Grind 54 2.3.2.6 Scrap 55 2.4 Cost of FO-WLP versus Wire Bond and Flip Chip 55 2.5 Package-on-Package Cost Analysis 61 2.5.1.1 Substrate/RDLs 63 2.5.1.2 Die Bond 63 2.5.1.3 CUF and Mold Cost 63 2.5.1.4 Ball Attach 64 2.5.1.5 Singulation 64 2.5.1.6 TMV 64 2.5.1.7 Die Bond 66 2.5.1.8 CUF and Mold Cost 66 2.5.1.9 TMV/Large Copper Pillars 66 2.6 Conclusions 66 References 67 3 Integrated Fan-Out (InFO) for Mobile Computing 69 Doug C.H. Yu, John Yeh, Kuo-Chung Yee, and Chih Hang Tung 3.1 Introduction 69 3.2 Fan-InWafer-Level Packaging 70 3.2.1 Dielectric and Redistribution Layers (RDL) 71 3.2.2 Under Bump Metallization (UBM) 71 3.2.3 Reliability and Challenges 72 3.2.4 Large Die WLP 72 3.3 Fan-OutWafer-Level System Integration 73 3.3.1 Chip-First vs. Chip-Last 74 3.3.2 Molding and Planarization 75 3.3.3 Redistribution Layer (RDL) 77 3.3.4 Through Via and Vertical Interconnection 80 3.4 Integrated Passive Devices (IPDs) 81 3.4.1 High Q-Factor 3D Solenoid Inductor 81 3.4.2 Antenna in Package (AiP) and 5G Communication 81 3.4.3 Passive Devices for MillimeterWave System Integration 82 3.5 Power, Performance, Form Factor, and Cost 85 3.5.1 Signal and Power Integrity 87 3.5.2 Heat Dissipation and Thermal Performance 88 3.5.3 Form Factor and Thickness 91 3.5.4 Cycle Time to Market and Cost 91 3.6 Summary 91 References 92 4 Integrated Fan-Out (InFO) for High Performance Computing 95 Doug C.H. Yu, John Yeh, Kuo-Chung Yee, and Chih Hang Tung 4.1 Introduction 95 4.2 3DFabric and System-on-Integrated-Chip (SoIC) 97 4.3 CoWoS-R, CoWoS-S, and CoWoS-L 99 4.4 InFO-L and InFO-R 100 4.5 Info Ultra-High-Density Interconnect (InFO-UHD) 100 4.6 Multi-Stack System Integration (MUST) and Must-in-Must (MiM) 106 4.7 InFO on Substate (InFO-oS) and InFO Local Silicon Interconnect (InFO-L) 108 4.8 InFO with Memory on Substrate (InFO-MS) 110 4.9 InFO 3D Multi-Silicon (InFO-3DMS) and CoWoS-L 111 4.10 InFO System onWafer (InFO_SoW) 112 4.11 System on Integrated Substrate (SoIS) 116 4.12 Immersion Memory Compute (ImMC) 116 4.13 Summary 121 References 122 5 Adaptive Patterning and M-Series for High Density Integration 125 Benedict San Jose, Cliff Sandstrom, Jan Kellar, Craig Bishop, and Tim Olson 5.1 Technology Description 125 5.2 Applications and Markets 127 5.3 Basic Package Construction 127 5.4 Manufacturing Process Flow and BOM 131 5.5 Design Features and System Integration Capability 134 5.6 Adaptive Patterning 137 5.7 Manufacturing Format and Scalability 144 5.8 Package Performance 149 5.9 Robustness and Reliability Data 151 5.10 Electrical Test Considerations 152 5.11 Summary 153 References 153 6 Panel-Level Packaging for Heterogenous Integration 155 M. Töpper, T. Braun, M. Billaud, and L. Stobbe 6.1 Introduction 155 6.2 Fan-Out Panel-Level Packaging 157 6.3 Economic Efficiency Analysis of PLP 161 6.4 Summary 165 References 166 7 Next Generation Chip Embedding Technology for High Efficiency Power Modules and Power SiPs 169 Vikas Gupta, Kay Essig, C.T. Chiu, and Mark Gerber 7.1 Technology Description 169 7.2 Basic Package Construction 172 7.3 Applications and Markets (HPC, SiP) 176 7.4 Manufacturing Process Flow and BOM 177 7.5 Design Features 180 7.6 System Integration Capability 182 7.7 Package Performance 183 7.8 Robustness and Reliability Data 186 7.9 Electrical Test Considerations 190 7.10 Summary 191 References 192 8 Die Integration Technologies on Advanced Substrates Including Embedding and Cavities 193 Markus Leitgeb and Christian Vockenberger 8.1 Introduction 193 8.2 Heterogeneous Integration by Use of Embedded Chip Packaging (ECP®) 194 8.3 Embedding Process 196 8.4 Component Selection 198 8.5 Design Technology 199 8.6 Testing 200 8.7 Applications for ECP Technology 201 8.8 Heterogeneous Integration Using Cavities in PCB 206 8.9 Package Performance, Robustness, and Reliability 208 8.10 Conclusion 215 References 215 9 Advanced Embedded Trace Substrate – A Flexible Alternative to Fan-Out Wafer Level Packaging 217 Shih Ping Hsu, Byron Hsu, and Adan Chou 9.1 Technology Description 217 9.1.1 C2iM Technology 217 9.1.2 C2iM-PLP Technology 218 9.2 Applications and Markets 219 9.3 Basic Package Construction 219 9.3.1 C2iM-PLP Experience 219 9.3.2 C2iM-PLP Advantages and Disadvantages Compared to Wirebond Quad Flat No Lead (WB-QFN) and Flip-Chip QFN (FC-QFN) Packages 219 9.3.3 C2iM-PLP Advantages and Disadvantages Compared to WLP and FO-WLP 220 9.3.4 Future Applications 222 9.3.5 Limitations of C2iM-PLP 222 9.4 Manufacturing Process Flow and BOM 223 9.5 Design Features 224 9.5.1 Package Design Rules 224 9.5.2 Design Rules for Die UBM 224 9.5.3 Design Rules for Die Side by Side 225 9.5.4 Design Rules for Cu Pillar 226 9.6 System Integration Capability 227 9.7 Manufacturing Format and Scalability 228 9.8 Package Performance 228 9.8.1 Electrical Performance 228 9.8.2 Thermal Performance 229 9.9 Robustness and Reliability Data 229 9.9.1 Automotive Reliability Certification Pass 229 9.9.2 Board Level Reliability Verification Pass 230 9.10 Electrical Test Considerations 230 9.11 Summary 231 References 231 10 Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging 233 Subramanian S. Iyer and Arsalan Alam 10.1 Introduction 233 10.2 Recent Trends in Packaging 239 10.3 FHE Using FO-WLP – FlexTrateTM 242 10.4 Applications on FlexTrateTM 250 Acknowledgments 256 References 256 11 Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations 261 Ting Zheng, Ankit Kaul, Sreejith Kochupurackal Rajan, and Muhannad S. Bakir 11.1 Introduction 261 11.2 Heterogeneous Interconnect Stitching Technology (HIST) 262 11.3 Thermal Evaluation of 2.5D Integration Using Bridge-Chip Technology 270 11.3.1 2.5D and 3D Benchmark Architectures 270 11.3.1.1 2.5D Integration 270 11.3.1.2 3D Integration 271 11.3.2 Thermal Modeling and Specifications 272 11.3.3 Comparison of Different 2.5D Integration Schemes 273 11.3.4 Thermal Comparison between 2.5D and 3D Integration 273 11.3.5 Thermal Study of Bridge-Chip 2.5D Integration 274 11.3.5.1 Impact of TIM conductivity 274 11.3.5.2 Die Thickness 275 11.3.5.3 Die Spacing 275 11.3.6 Polylithic 3D Integration 275 11.4 Monolithic Microfluidic Cooling of High-Power Electronics 276 11.4.1 Experimental Demonstration and Characterization on Single Die Systems 277 11.4.2 Microfluidic Cooling of 2.5D Devices: Experimental Demonstration 279 11.4.3 Monolithic Microfluidic Cooling of 3D Integration: Modelling Electrical Implications for I/Os 281 11.5 Conclusion 283 Acknowledgments 283 References 283 Index 289


Best Sellers


Product Details
  • ISBN-13: 9781119793779
  • Publisher: John Wiley & Sons Inc
  • Publisher Imprint: Wiley-IEEE Press
  • Height: 10 mm
  • No of Pages: 320
  • Series Title: IEEE Press
  • Sub Title: High Performance Compute and System-in-Package
  • Width: 10 mm
  • ISBN-10: 1119793777
  • Publisher Date: 04 Jan 2022
  • Binding: Hardback
  • Language: English
  • Returnable: N
  • Spine Width: 10 mm
  • Weight: 639 gr


Similar Products

How would you rate your experience shopping for books on Bookswagon?

Add Photo
Add Photo

Customer Reviews

REVIEWS           
Click Here To Be The First to Review this Product
Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package(IEEE Press)
John Wiley & Sons Inc -
Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package(IEEE Press)
Writing guidlines
We want to publish your review, so please:
  • keep your review on the product. Review's that defame author's character will be rejected.
  • Keep your review focused on the product.
  • Avoid writing about customer service. contact us instead if you have issue requiring immediate attention.
  • Refrain from mentioning competitors or the specific price you paid for the product.
  • Do not include any personally identifiable information, such as full names.

Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package(IEEE Press)

Required fields are marked with *

Review Title*
Review
    Add Photo Add up to 6 photos
    Would you recommend this product to a friend?
    Tag this Book
    Read more
    Does your review contain spoilers?
    What type of reader best describes you?
    I agree to the terms & conditions
    You may receive emails regarding this submission. Any emails will include the ability to opt-out of future communications.

    CUSTOMER RATINGS AND REVIEWS AND QUESTIONS AND ANSWERS TERMS OF USE

    These Terms of Use govern your conduct associated with the Customer Ratings and Reviews and/or Questions and Answers service offered by Bookswagon (the "CRR Service").


    By submitting any content to Bookswagon, you guarantee that:
    • You are the sole author and owner of the intellectual property rights in the content;
    • All "moral rights" that you may have in such content have been voluntarily waived by you;
    • All content that you post is accurate;
    • You are at least 13 years old;
    • Use of the content you supply does not violate these Terms of Use and will not cause injury to any person or entity.
    You further agree that you may not submit any content:
    • That is known by you to be false, inaccurate or misleading;
    • That infringes any third party's copyright, patent, trademark, trade secret or other proprietary rights or rights of publicity or privacy;
    • That violates any law, statute, ordinance or regulation (including, but not limited to, those governing, consumer protection, unfair competition, anti-discrimination or false advertising);
    • That is, or may reasonably be considered to be, defamatory, libelous, hateful, racially or religiously biased or offensive, unlawfully threatening or unlawfully harassing to any individual, partnership or corporation;
    • For which you were compensated or granted any consideration by any unapproved third party;
    • That includes any information that references other websites, addresses, email addresses, contact information or phone numbers;
    • That contains any computer viruses, worms or other potentially damaging computer programs or files.
    You agree to indemnify and hold Bookswagon (and its officers, directors, agents, subsidiaries, joint ventures, employees and third-party service providers, including but not limited to Bazaarvoice, Inc.), harmless from all claims, demands, and damages (actual and consequential) of every kind and nature, known and unknown including reasonable attorneys' fees, arising out of a breach of your representations and warranties set forth above, or your violation of any law or the rights of a third party.


    For any content that you submit, you grant Bookswagon a perpetual, irrevocable, royalty-free, transferable right and license to use, copy, modify, delete in its entirety, adapt, publish, translate, create derivative works from and/or sell, transfer, and/or distribute such content and/or incorporate such content into any form, medium or technology throughout the world without compensation to you. Additionally,  Bookswagon may transfer or share any personal information that you submit with its third-party service providers, including but not limited to Bazaarvoice, Inc. in accordance with  Privacy Policy


    All content that you submit may be used at Bookswagon's sole discretion. Bookswagon reserves the right to change, condense, withhold publication, remove or delete any content on Bookswagon's website that Bookswagon deems, in its sole discretion, to violate the content guidelines or any other provision of these Terms of Use.  Bookswagon does not guarantee that you will have any recourse through Bookswagon to edit or delete any content you have submitted. Ratings and written comments are generally posted within two to four business days. However, Bookswagon reserves the right to remove or to refuse to post any submission to the extent authorized by law. You acknowledge that you, not Bookswagon, are responsible for the contents of your submission. None of the content that you submit shall be subject to any obligation of confidence on the part of Bookswagon, its agents, subsidiaries, affiliates, partners or third party service providers (including but not limited to Bazaarvoice, Inc.)and their respective directors, officers and employees.

    Accept

    New Arrivals


    Inspired by your browsing history


    Your review has been submitted!

    You've already reviewed this product!
    ASK VIDYA